Ferroelectric, non-volatile memories have memory cells consisting of a selection transistor, or access transistor, and, connected in series to the selection transistor, a storage capacitor whose dielectric is formed by a film of ferroelectric material.
Applying an electric field of sufficient intensity to the storage capacitor, the ferroelectric material becomes polarized in the direction of the electric field, and, thus, the polarization achieved is also maintained after the electric field is removed. If, at a later time, an electric field is applied to the storage capacitor having sufficient intensity and direction opposite to the direction of the polarization previously achieved, the ferroelectric material becomes polarized in the opposite direction and remains polarized in such opposite direction even after the removal of the electric field. The polarization of the ferroelectric material has the effect of producing a nonzero, electric charge for unit storage capacitor area, and such a charge persists even when no voltage is applied to the capacitor and does not disappear with time.
A binary information (bit) can, thus, be stored in the memory cell, by associating the two logic states, “1” and “0”, with the two opposite polarization directions of the storage capacitor.
Ferroelectric memories are also called ferroelectric RAMs or FeRAMs, due to the similarities of their memory cells with the memory cells of a dynamic RAM (DRAM), which, as known, are also formed by a transistor and a capacitor connected in series.
Two families of FeRAMs are known, mainly differing from one another in the number of memory cells employed for storing a single bit.
The FeRAMs belonging to a first family use a single memory cell as a bit storage unit, or memory unit; for this reason, these FeRAMs are also called “1T1C” (standing for one transistor, one capacitor). Thanks to the simplicity of their memory units, these memories can have very large size, of the order of the megabits.
The FeRAMs of a second family employ two memory cells as a memory unit; for this reason, the FeRAMs of this second family are called “2T2C” (two transistors, two capacitors). The 2T2C FeRAMs occupy more area than the 1T1C FeRAMs, but the operation of data reading is less complicated compared to 1T1C FeRAMs, because one of the two cells of a memory unit acts as a reference signal generator for the other cell.
As in other memory devices, the memory cells in FeRAMs are arranged by rows and columns, to form a matrix. Each memory cell has the gate of the respective selection transistor connected to a word line of the matrix, the drain of the selection transistor connected to a bit line of the matrix and the free plate of the respective storage capacitor connected to a plate biasing line (shortly, a plate line) of the matrix.
According to a suitable arrangement of the matrix, the memory cells belonging to a same row of the matrix share the same word line and the same plate line; the memory cells belonging to a same column of the matrix share the same bit line.
Accessing a memory cell for reading the datum contained therein is an operation that comprises a succession of phases. In a first phase, also referred to as pre-charge phase, the bit line and the plate line associated with the cell to be read are biased to prescribed initial electric potentials, typically to the reference potential of the memory (ground); in this phase, the electric potential of the word line associated with the memory cell is also kept to ground. Subsequently, the potential of the word line is raised to a prescribed value, for instance corresponding to the supply voltage of the memory (VDD); in this way, the selection transistor of the memory cell is turned on, connecting a plate of the storage capacitor to the bit line. Then, the potential of the plate line is also raised to VDD: this causes an electric potential to be established on the bit line, such electric potential depending on the polarization state of the storage capacitor. A read phase follows, in which the read circuits sense the electric potential that has been established on the bit line, and properly amplify it.
The following phase, also called restore phase, is directed to restoring the datum initially contained in the memory cell; it is, in fact, known that reading an FeRAM memory cell in a given polarization state destroys the datum stored therein, because the storage capacitor is brought into a final polarization state opposite to the initial polarization state. In a “1T1C” memory unit, the destruction of the datum only occurs if the cell is initially in one of the two possible states, while in a “2T2C” memory unit the destruction of the datum always takes place, because the two cells making up the memory unit are always in initially opposed states.
In the restore phase, after having brought the potential of the bit line to ground or to VDD, depending on the polarization state of the storage capacitor, the plate line is brought to ground; since the electric potential applied to the bit line in the case in which the storage capacitor has experienced a polarization state transition is equal to VDD, an electric field favorable to the re-estabslishment (restore) of the initial polarization state is applied to the storage capacitor.
In the final phase of the read operation, all the electric potentials of the different lines are reset to the initial state.
In the data restore phase, the selection transistors have to be properly overdriven, so as to be capable of transferring to the storage capacitors the full voltage that the read circuits place on the bit lines. In particular, in order to be capable of transferring the full voltage VDD to the plate of the respective storage capacitor, the gate of a selection transistor must be driven to a voltage at least equal to (VDD+Vth), where Vth denotes the threshold voltage of the selection transistor.
Several techniques are known for overdriving the selection transistors; all these techniques can, however, be classified according to three principles.
A first solution calls for integrating, in the memory, charge pumps that, starting from the supply voltage VDD, generate a higher voltage, fed to the word line that, in the restore phase, is selected so as to be accessed.
The disadvantage of such solution resides in that the semiconductor chip area is occupied by the charge pumps that include capacitors, diodes, a generator of phases for driving the capacitors and an output voltage regulator. Further, area needs to be reserved for the routing of the lines necessary to bring the output voltage of the charge pumps to the word lines. Another drawback is the power consumption of these circuits; in order to limit such power consumption, it is necessary to implement charge pump turn-off and turn-on schemes, that, however, contribute to increasing the area occupied.
A second solution calls for integrating voltage boost capacitors, one for each word line or for a group of word lines. Charging to the voltage VDD the capacitor associated with the word line to be boosted, and then raising the potential of the free plate of the capacitor, it is possible to raise the word line potential enough so as to overdrive the selection transistors.
Also, this solution has the disadvantage of involving a great waste of area.
A third solution relies on the bootstrap effect that is induced on the word line voltage by the raising of the bit line voltage. Such effect takes place thanks to the capacitive coupling between the bit line and the word line, and, therefore, allows raising the word line electric potential enough so that the selection transistor can transfer the full voltage VDD present on the bit line to the ferroelectric capacitor.
This last solution is the least expensive from the point of view of chip area and power consumption because it does not require additional circuitry; neither does it require further area to be reserved for the routing of the voltage generated by the charge pumps. Nevertheless, this solution poses limitations to the design of the memory cells arrangement.
In fact, the boostrap effect takes place thanks to the electric charge partition between the equivalent capacitance seen by the bit line toward the selected word line, and the word line capacitance. Such charge partition takes place when the bit line is brought to the voltage VDD, which happens when the storage capacitor connected to the bit line changes the polarization state thereof.
In order to ensure that the bootstrap effect is not frustrated by the presence, on the same word line, of non-accessed memory units, the length of the word line has to coincide with the length of the plate line. This contrasts with the desire of being able to selectively access only some memory units of the word line so as not to cause an unnecessary fatigue on the memory units that do not need to be read.